1. Field of the Invention
The present invention relates to a dynamic random access memory device having a self-refresh function and, more specifically, it relates to a random access memory device capable of performing a self-refresh operation without a malfunction.
2. Description of the Prior Art
FIG. 1A is a block diagram showing an example of a simplified circuit of a conventional 1 M bit dynamic RAM (Random Access Memory) having 1048576 memory cells. Referring to FIG. 1A, a summary of the basic operation of the dynamic RAM and the "CAS before RAS Refresh" function in relation to the present invention will be hereinafter described.
A clock generator 151 receives an RAS (Row Address Strobe) signal, CAS (Column Address Strobe) signal and WE (Write Enable) signal from a CPU (Central Processing Unit) and generates clock signals .phi..sub.0 and .phi..sub.1. In the normal read/write operation of the dynamic RAM, an address buffer 1 receives external address signals EXT. A.sub.0 to A.sub.9 on a time share basis through a switching circuit 4 and applies internal address signals A.sub.0 to A.sub.8 on a time share basis to a row decoder 155 and a column decoder 156. The row decoder 155 and the column decoder 156 decode the internal address signals A.sub.0 to A.sub.8 and apply the decoded signals to a memory cell array 158 and an I/O gates 157. The writing operation of the input data D.sub.IN and the reading operation of the output data D.sub.OUT are carried out for a memory cell having the address designated as described above. An input buffer 159 receives the input data D.sub.IN and transfers the input data D.sub.IN to the memory cell array 158 via the I/0 gates 157 and the sense amplifiers 163 in response to a clock signal .phi..sub.3. On the other hand, the output buffer 160 receives the data from the memory cell array 158 via the sense amplifiers 163 and the I/O gates 157 and outputs the output data D.sub.OUT in response to the clock signal .phi..sub.3.
In the dynamic RAM, as is generally known, the reading and rewriting operation of all the memory cells, that is, the refresh operation, is carried out during the intervals of the above described usual read/write operation. Referring to FIG. 1A, in a refresh operation a refresh controller 152 generates a driving signal T for driving a refresh counter 2 in response to a clock signal .phi..sub.0 from the clock generator 151. The refresh counter 2 receives the driving signal T and performs count operation and applies the output signals Q.sub.0 to Q.sub.8 to the address buffer 1 through the switching circuit 4. The address buffer 1 receives the output signals Q.sub.0 to Q.sub.8 of the refresh counter 2 instead of the external address signals EXT. A.sub.0 to A.sub.8 through the switching circuit 4 and applies the same as the internal address signals A.sub.0 to A.sub.8 to the row decoder 155. In the memory cell array 158, the reading operation of already written data and the rewriting operation are carried out successively for the memory cells having the addresses designated by the internal address signals A.sub.0 to A.sub.8. Since the refresh counter 2 successively outputs the output signals, the refresh of all memory cells can be accomplished by the repetition of the above described operation.
As described above, the method for performing refreshing, in which the signals for refreshing are not applied externally as the external address signals EXT. A.sub.0 to EXT. A.sub.9 but the signals are generated by the refresh counter 2 provided in the chip, is called "CAS before RAS Refresh", which is an almost standard function of a dynamic RAM.
In the block diagram of the dynamic RAM shown in FIG. 1A, the switching circuit 4 selects either the external address signals EXT. A.sub.0 to EXT A.sub.8 or the output signals Q.sub.0 to Q.sub.8 of the refresh counter 2 in response to the clock signals .phi..sub.2 and .phi..sub.2 and applies the same to the address buffer 1.
Publications concerning the dynamic RAMs having the above described internal refresh function are seen in the paper of S. S. Eaton et al. in IEEE International Solid-State Circuits Conference held on February 15, 1979 and in the article of D. C. Ford et al. recited in ELECTRONICS published on Feb. 15, 1979.
An application of the prior art of particular interest to the present application concerning a dynamic memory device having internal refresh function is seen in U.S. Pat. No. 4,207,618 entitled "ON-CHIP REFRESH FOR DYNAMIC MEMORY", issued to L. S. White, Jr. et al. on June 10, 1980.
As described above, the operation state of the dynamic RAM comprises the normal read/write operation stat, "CAS before RAS Refresh" operation state and, further a standby state which is the state other than the above mentioned two operation states of the dynamic RAM. These three states are specified by the RAS signal and the CAS signal.
FIG. 1B is a timing chart showing the relation between the RAS signal, CAS signal and other signals and the three states of the dynamic RAM. Referring to FIG. 1B, the clock signals .phi..sub.2 and .phi..sub.2 are the signals required for the operation of the switching circuit 4 and they are applied to the switching circuit 4 from the clock generator 151 through the refresh controller 152.
Referring to the timing chart of FIG. 1B, when the RAS signal and the CAS signal simultaneously become high level, the dynamic RAM is in the standby state. On this occasion, the clock signals .phi..sub.2 and .phi..sub.2 have the voltages of low level and high level, respectively. Meanwhile when the CAS signal becomes low level and thereafter the RAS signal becomes low level, the "CAS before RAS Refresh" operation starts in the dynamic RAM. On this occasion both inverted clock signals .phi..sub.2 and .phi..sub.2 are applied to the switching circuit 4. When the dynamic RAM is in the standby state initially, and the CAS signal becomes low level after the RAS signal becomes low level, the normal read/write operation of the dynamic RAM starts. When the RAS signal is at the low level, it is called the activated state.
FIG. 2A is a schematic diagram showing the conventional switching circuit 4 and the peripheral circuits thereof shown in FIG. 1A. FIG. 2A comprises nine circuit portions having similar connections. In the following, the description will be made only of the i-th circuit portion for the simplicity of the description, and the description can be applied to other circuit portions.
Referring to FIG. 2A, an input terminal 9 for receiving the i-th external address signal EXT. Ai is connected to one input of the switching circuit 4 through an n type field effect transistor 3. A clock signal .phi..sub.1 is applied to the gate of the transistor 3 from the clock generator. The clock signal .phi..sub.1 becomes high level in the standby state. The refresh counter 2 is connected to the other input of the switching circuit 4. The output of the switching circuit 4 is connected to the address buffer 1. The switching circuit 4 comprises an n type field effect transistor 40 connected to the transistor 3 and an n type field effect transistor 41 connected to the refresh counter 2. The node of the transistors 40 and 41 constitute the output of the switching circuit 4. A clock signal .phi..sub.2 is applied to the gate of the transistor 41 and the inverted signal .phi..sub.2 of the clock signal .phi..sub.2 is applied to the gate of the transistor 40, respectively. The clock signals .phi..sub.2 and .phi..sub.2 are applied to the transistors 40 and 41 both from the clock generator through the refresh controller. In the refresh counter 2, a series connection in the output stage of the n type field effect transistors 20 and 21 connected between the power supply V.sub.cc and the ground V.sub.ss is schematically shown. In the address buffer 1, an n type MOS field effect transistor 10 in the input stage and a capacitor 11 for holding voltage are schematically shown. The address buffer 1 outputs the i-th internal address signal A.sub.i out of 0 to 9 and the inverted signal thereof, A.sub.i. V.sub.b denotes the voltage of the input of the address buffer 1. Q.sub.i is the i-th output signal of the refresh counter 2.
In the circuit of FIG. 2A, the switching circuit 4 selectively applies either the external address signal EXT. Ai or the output signal Q.sub.i of the refresh counter to the input of the address buffer 1 in response to the clock signals .phi..sub.2 and .phi..sub.2.
The operation will be described. In the following, the supply level of the voltage will be described as the H level while the ground level of the voltage will be described as the L level.
FIG. 2B is a timing chart showing the changes in each of the signals in the i-th circuit portion of the circuit shown in FIG. 2A. Referring to FIG. 2B, at time t.sub.1, the clock signal .phi..sub.1 is at the H level, the clock signal .phi..sub.2 is at the L level and the clock signal .phi..sub.2 is at the H level, so that the external address signal EXT. Ai is applied to the input of the address buffer 1 through the transistor 40 of the switching circuit 4. At time t.sub.1, let us assume that the voltage of the external address signal EXT. Ai is 0 volt. The input of the address buffer 1 is brought to the voltage of 0 volt (reference should be made to the waveform of V.sub.b in FIG. 2B). At time t.sub.2, when the clock signal .phi..sub.2 changes to the H level and the clock signal .phi..sub.2 changes to the L level, the transistor 40 turns off in response to the clock signal .phi..sub.2 while the transistor 41 turns on in response to the clock signal .phi..sub.2. Therefore, the input of the address buffer 1 receives the output signal Q.sub.i of the refresh counter 2 instead of the external address signal EXT. Ai through the switching circuit 4. At time t.sub.2, when the output signal Q.sub.i of the refresh counter 2 is at the H level, the input voltage V.sub.b of the address buffer 1 begins to rise (reference should be made to the waveform of V.sub.b of FIG. 2B). At time t.sub.3, the address buffer 1 starts the operation. At time t.sub.3, the input of the address buffer 1 receives the H level output 15 signal from the refresh counter 2 and is brought to the voltage near V.sub.b = V.sub.cc -V.sub.th, where V.sub.cc is the supply voltage and V.sub.th is the value of the larger one of the threshold voltages of the transistors 20 and 41.
In the preceding paragraph, it was assumed that at time t.sub.1, that EXT. A; was at zero volts. However, since EXT. A is an externally applied signal, in practice, EXT. A, can assume a lower voltage representing the low logic level. This is because the external circuit supplying EXT. A, may be operated at a slightly different supply voltage or the signal may contain noise. Such an occurrence is well-recognized and memories are commonly rated at a -1.0 to -2.0 volt lower limit to be recognized as a low logic level.
Accordingly, at time t.sub.1, let us assume that the voltage of the external address signal EXT. Ai is for example -2.0 volt, which is the lowest voltage enabling the external address signal EXT. Ai to be recognized as the logic low level. The input of the address buffer 1 is brought to the voltage of -2.0 volt (reference should be made to the dotted line in FIG. 2B). After the time t.sub.2, in the similar manner as described above, the input of the address buffer 1 is brought to the voltage near V.sub.b =V.sub.cc -V.sub.th in response to the H level output signal from the refresh counter 2. However, sometimes the input voltage V.sub.b of the address buffer 1 is not brought to the voltage which can be recognized by the address buffer 1 as the logic high level at the time t.sub.3, that is, the time when the address buffer 1 begins the operation. As a result, since the address buffer 1 can not receive the correct signal from the refresh counter 2, the "CAS before RAS Refresh" operation, for example, is not carried out correctly.
The capacitor 11 of the address buffer 1 is to maintain the voltage of the external address signal EXT. Ai applied to the input of the address buffer 1. Namely, when the voltage of the external address signal EXT. Ai is applied to the input of the address buffer 1, the capacitor 11 is charged. Thereafter, the transistor 3 turns off in response to the clock signal .phi..sub.1 and the input of the address buffer 1 is brought to the floating state. The capacitor 11 continues to apply the charged voltage to the gate of the transistor 10 during the operation of the address buffer 1. Therefore, the external address signal EXT. Ai need not be continuously applied to the input terminal 9.